CCD 信號處理器
Overview:
- 16 bit signal processer Analog-Front-End (AFE) for digitizing analog outputs from CCD sensors.
- Both 2-in-1 (AFE + horizontal timing generator, driver + vertical driver) and 3-in-1 (AFE + horizontal timing generator, driver + programable vertical timing generator, driver) are available.
Features:
- CCD Signal Processing: Correlated Double Sampling (CDS) and Sample Hold
- Integrated Vertical CCD driver:
- 27 channel V-driver with SUB driver
- 3 level driver connected to VM2 : 10 channel
- 3 level driver connected to VM : 4 channel
- Small 3 level driver connected to VM : 1 channel
- 2 level driver: 6 channel(Large) + 6 channel (Small)
- 3 level driver: 1 channel SUB driver
- On-chip boost-circuit for SUB driver
- Programmable gain amp (PGA): -3dB,0db,3db,6db,9db,12db,15db, and 18dB by analog gain 0dB to 36db by digital gain
- 16 Bit 50MHz internal Analog to Digital Converter(ADC)
- 12bit or 14bit parallel output resolution
- 82dB input referred SNR with 12dB-analog-gain
- Adjustable Optical Black Clamp level
- Internal CLPOB/CLPDM/HBLK Signal Generator
- RG and Horizontal driver 4phase, 1.8V-3.0V Horizontal driver
- 1 LH driver and 1 RG driver
- Precision timing generator for RG and H drivers
- 6-channel Universal IO for strobe and any system control (3-in-1)
- Bank system for replacing program code (3-in1)
Function Block:
Block Diagram of 2-in-1
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Block Diagram of 3-in-1
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